| Opcode/Instruction | Op/En | 64/32 bit Mode Support | CPUID Feature Flag | Description |
|---|---|---|---|---|
| EAX = 03H ENCLS[EREMOVE] | IR | V/V | SGX1 | This leaf function removes a page from the EPC. |
| Op/En | EAX | RCX |
| IR | EREMOVE (In) | Effective address of the EPC page (In) |
This leaf function causes an EPC page to be un-associated with its SECS and be marked as unused. This instruction leaf can only be executed when the current privilege level is 0.
The content of RCX is an effective address of an EPC page. The DS segment is used to create linear address. Segment override is not supported.
The instruction fails if the operand is not properly aligned or does not refer to an EPC page or the page is in use by another thread, or other threads are running in the enclave to which the page belongs. In addition the instruction fails if the operand refers to an SECS with associations.
| EPCPAGE |
| Write access permitted by Enclave |
The instruction faults if any of the following:
| The memory operand is not properly aligned. | The memory operand does not resolve in an EPC page. |
| Refers to an invalid SECS. | Refers to an EPC page that is locked by another thread. |
| Another Intel SGX instruction is accessing the EPC page. | RCX does not contain an effective address of an EPC page. |
| the EPC page refers to an SECS with associations. |
The error codes are:
| Error Code (see Table 40-4) | Description |
|---|---|
| No Error | EREMOVE successful. |
| SGX_CHILD_PRESENT | If the SECS still have enclave pages loaded into EPC. |
| SGX_ENCLAVE_ACT | If there are still logical processors executing inside the enclave. |
| Leaf | Parameter | Base Concurrency Restrictions | ||
|---|---|---|---|---|
| Access | On Conflict | SGX_CONFLICT VM Exit Qualification | ||
| EREMOVE | Target [DS:RCX] | Exclusive | #GP | EPC_PAGE_CONFLICT_EXCEPTION |
| Leaf | Parameter | Additional Concurrency Restrictions | |||||
|---|---|---|---|---|---|---|---|
| vs. EACCEPT, EACCEPTCOPY, EMODPE, EMODPR, EMODT | vs. EADD, EEXTEND, EINIT | vs. ETRACK, ETRACKC | |||||
| Access | On Conflict | Access | On Conflict | Access | On Conflict | ||
| EREMOVE | Target [DS:RCX] | Concurrent | Concurrent | Concurrent | |||
| Name | Type | Size (Bits) | Description |
|---|---|---|---|
| TMP_SECS | Effective Address | 32/64 | Effective address of the SECS destination page. |
IF (DS:RCX is not 4KByte Aligned)
THEN #GP(0); FI;
IF (DS:RCX does not resolve to an EPC page)
THEN #PF(DS:RCX); FI;
TMP_SECS ← Get_SECS_ADDRESS();
(* Check the EPC page for concurrency *)
IF (EPC page being referenced by another Intel SGX instruction)
THEN
IF (<<VMX non-root operation>> AND <<ENABLE_EPC_VIRTUALIZATION_EXTENSIONS>>)
THEN
VMCS.Exit_reason ← SGX_CONFLICT;
VMCS.Exit_qualification.code ← EPC_PAGE_CONFLICT_EXCEPTION;
VMCS.Exit_qualification.error ← 0;
VMCS.Guest-physical_address←<< translation of DS:RCX produced by paging >>;
VMCS.Guest-linear_address ← DS:RCX;
Deliver VMEXIT;
ELSE
#GP(0);
FI;
FI;
(* if DS:RCX is already unused, nothing to do*)
IF ( (EPCM(DS:RCX).VALID = 0) or (EPCM(DS:RCX).PT = PT_TRIM AND EPCM(DS:RCX).MODIFIED = 0))
THEN GOTO DONE;
FI;
IF ( (EPCM(DS:RCX).PT = PT_VA) OR
((EPCM(DS:RCX).PT = PT_TRIM) AND (EPCM(DS:RCX).MODIFIED = 0)) )
THEN
EPCM(DS:RCX).VALID ← 0;
GOTO DONE;
FI;
IF (EPCM(DS:RCX).PT = PT_SECS)
THEN
IF (DS:RCX has an EPC page associated with it)
THEN
RFLAGS.ZF ← 1;
RAX← SGX_CHILD_PRESENT;
GOTO ERROR_EXIT;
FI;
(* treat SECS as having a child page when VIRTCHILDCNT is non-zero *)
IF (<<in VMX non-root operation>> AND
<<ENABLE_EPC_VIRTUALIZATION_EXTENSIONS>> AND
(SECS(DS:RCX).VIRTCHILDCNT ≠ 0))
THEN
RFLAGS.ZF ← 1;
RAX ← SGX_CHILD_PRESENT
GOTO ERROR_EXIT
FI;
EPCM(DS:RCX).VALID ← 0;
GOTO DONE;
FI;
IF (Other threads active using SECS)
THEN
RFLAGS.ZF ← 1;
RAX← SGX_ENCLAVE_ACT;
GOTO ERROR_EXIT;
FI;
IF ( (EPCM(DS:RCX).PT is PT_REG) or (EPCM(DS:RCX).PT is PT_TCS) or (EPCM(DS:RCX).PT is PT_TRIM) )
THEN
EPCM(DS:RCX).VALID ← 0;
GOTO DONE;
FI;
DONE:
RAX← 0;
RFLAGS.ZF ← 0;
ERROR_EXIT:
RFLAGS.CF,PF,AF,OF,SF ← 0;
Sets ZF if unsuccessful, otherwise cleared and RAX returns error code. Clears CF, PF, AF, OF, SF.
| #GP(0) | If a memory operand effective address is outside the DS segment limit. |
| If a memory operand is not properly aligned. | |
| If another Intel SGX instruction is accessing the page. | |
| #PF(error | code) If a page fault occurs in accessing memory operands. |
| If the memory operand is not an EPC page. |
| #GP(0) | If the memory operand is non-canonical form. |
| If a memory operand is not properly aligned. | |
| If another Intel SGX instruction is accessing the page. | |
| #PF(error | code) If a page fault occurs in accessing memory operands. |
| If the memory operand is not an EPC page. |