| Opcode/Instruction | Op/En | 64/32 bit Mode Support | CPUID Feature Flag | Description |
|---|---|---|---|---|
| 66 0F 15 /r UNPCKHPD xmm1, xmm2/m128 | A | V/V | SSE2 | Unpacks and Interleaves double-precision floating-point values from high quadwords of xmm1 and xmm2/m128. |
| VEX.128.66.0F.WIG 15 /r VUNPCKHPD xmm1,xmm2, xmm3/m128 | B | V/V | AVX | Unpacks and Interleaves double-precision floating-point values from high quadwords of xmm2 and xmm3/m128. |
| VEX.256.66.0F.WIG 15 /r VUNPCKHPD ymm1,ymm2, ymm3/m256 | B | V/V | AVX | Unpacks and Interleaves double-precision floating-point values from high quadwords of ymm2 and ymm3/m256. |
| EVEX.128.66.0F.W1 15 /r VUNPCKHPD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst | C | V/V | AVX512VL AVX512F | Unpacks and Interleaves double precision floating-point values from high quadwords of xmm2 and xmm3/m128/m64bcst subject to writemask k1. |
| EVEX.256.66.0F.W1 15 /r VUNPCKHPD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst | C | V/V | AVX512VL AVX512F | Unpacks and Interleaves double precision floating-point values from high quadwords of ymm2 and ymm3/m256/m64bcst subject to writemask k1. |
| EVEX.512.66.0F.W1 15 /r VUNPCKHPD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst | C | V/V | AVX512F | Unpacks and Interleaves double-precision floating-point values from high quadwords of zmm2 and zmm3/m512/m64bcst subject to writemask k1. |
| Op/En | Tuple Type | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
| A | NA | ModRM:reg (r, w) | ModRM:r/m (r) | NA | NA |
| B | NA | ModRM:reg (w) | VEX.vvvv (r) | ModRM:r/m (r) | NA |
| C | Full | ModRM:reg (w) | EVEX.vvvv (r) | ModRM:r/m (r) | NA |
Performs an interleaved unpack of the high double-precision floating-point values from the first source operand and the second source operand. See Figure 4-15 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding ZMM register destination are unmodified. When unpacking from a memory operand, an implementation may fetch only the appropriate 64 bits; however, alignment to 16-byte boundary and normal segment checking will still be enforced.
VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register.
EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 64-bit memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.
EVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register, a 256-bit memory location, or a 256-bit vector broadcasted from a 64-bit memory location. The destination operand is a YMM register, conditionally updated using writemask k1.
EVEX.128 encoded version: The first source operand is a XMM register. The second source operand is a XMM register, a 128-bit memory location, or a 128-bit vector broadcasted from a 64-bit memory location. The destination operand is a XMM register, conditionally updated using writemask k1.
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF VL >= 128
TMP_DEST[63:0] ← SRC1[127:64]
TMP_DEST[127:64] ← SRC2[127:64]
FI;
IF VL >= 256
TMP_DEST[191:128] ← SRC1[255:192]
TMP_DEST[255:192] ← SRC2[255:192]
FI;
IF VL >= 512
TMP_DEST[319:256] ← SRC1[383:320]
TMP_DEST[383:320] ← SRC2[383:320]
TMP_DEST[447:384] ← SRC1[511:448]
TMP_DEST[511:448] ← SRC2[511:448]
FI;
FOR j←0 TO KL-1
i←j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i]←TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] ← 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] ← 0
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j←0 TO KL-1
i←j * 64
IF (EVEX.b = 1)
THEN TMP_SRC2[i+63:i]←SRC2[63:0]
ELSE TMP_SRC2[i+63:i]←SRC2[i+63:i]
FI;
ENDFOR;
IF VL >= 128
TMP_DEST[63:0] ← SRC1[127:64]
TMP_DEST[127:64] ← TMP_SRC2[127:64]
FI;
IF VL >= 256
TMP_DEST[191:128] ← SRC1[255:192]
TMP_DEST[255:192] ← TMP_SRC2[255:192]
FI;
IF VL >= 512
TMP_DEST[319:256] ← SRC1[383:320]
TMP_DEST[383:320] ← TMP_SRC2[383:320]
TMP_DEST[447:384] ← SRC1[511:448]
TMP_DEST[511:448] ← TMP_SRC2[511:448]
FI;
FOR j←0 TO KL-1
i←j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i]←TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] ← 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] ← 0
DEST[63:0] ←SRC1[127:64] DEST[127:64] ←SRC2[127:64] DEST[191:128]←SRC1[255:192] DEST[255:192]←SRC2[255:192] DEST[MAXVL-1:256] ←0
DEST[63:0] ←SRC1[127:64] DEST[127:64] ←SRC2[127:64] DEST[MAXVL-1:128] ←0
DEST[63:0] ←SRC1[127:64] DEST[127:64] ←SRC2[127:64] DEST[MAXVL-1:128] (Unmodified)
VUNPCKHPD __m512d _mm512_unpackhi_pd( __m512d a, __m512d b);
VUNPCKHPD __m512d _mm512_mask_unpackhi_pd(__m512d s, __mmask8 k, __m512d a, __m512d b);
VUNPCKHPD __m512d _mm512_maskz_unpackhi_pd(__mmask8 k, __m512d a, __m512d b);
VUNPCKHPD __m256d _mm256_unpackhi_pd(__m256d a, __m256d b)
VUNPCKHPD __m256d _mm256_mask_unpackhi_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);
VUNPCKHPD __m256d _mm256_maskz_unpackhi_pd(__mmask8 k, __m256d a, __m256d b);
UNPCKHPD __m128d _mm_unpackhi_pd(__m128d a, __m128d b)
VUNPCKHPD __m128d _mm_mask_unpackhi_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VUNPCKHPD __m128d _mm_maskz_unpackhi_pd(__mmask8 k, __m128d a, __m128d b);
None
Non-EVEX-encoded instructions, see Exceptions Type 4.
EVEX-encoded instructions, see Exceptions Type E4NF.